This invention relates to digital memories, and more particularly to circuits and methods for addressing binarily addressable digital memories with a binary coded decimal (BCD) address. Basically, a BCD address consists of a plurality of digits; and each of the digits consists of four bits. Those four bits have states of 0000, 0001 . . . 1001. All of the states above 1001 (i.e., 1010-1111) are undefined and do not occur. By comparison, the address inputs of a binarily addressable memory have no undefined states. That is, the address inputs of a binary addressable memory can vary from 000 . . . 0 to 111 . . . 1.
In the prior art when BCD addresses were utilized to address a binarily addressable memory, the BCD address was first sent through a BCD to binary converter. Then the binary output of the converter was utilized to address the memory. This is illustrated in FIG. 1. Specifically in that figure, the symbols D1-D6 indicate the various digits of the BCD address, letters A-L represent the bits in digits D1-D6, reference numeral 10 indicates the BCD to binary converter, and reference numeral 11 indicates the binarily addressable memory.
Included within the BCD to binary converter 10 are a plurality of binary adders 12-16, and a plurality of single digit decimal to binary encoders 17-21. Encoder 17 operates to encode digit D2 into the binary equivalent of a decimal 10, 20, . . . 90; encoder 18 operates to encode digit D3 into the binary equivalent of a decimal 100, 200, . . . 900; etc. All of the outputs of the encoders are summed by the adders 12-16 to obtain an address on a bus 22 which is the binary equivalent of the BCD address D6-D1. Data is sent on a bus 23 between the addressed memory location and the digital system 24 which formed the BCD address.
One problem with the above prior art circuit is that its operation is inherently slow. This is because the BCD memory address signals must pass through several levels of logic before they are converted to binary. For example, digit D3 must pass through components 18, 13, 15 and 16. Typically, the time required for all of the BCD signals to pass through converter 10 is so large that the digital system 24 must extend its normal cycle time whenever it addresses the memory 11.
Another problem with the FIG. 1 circuit is that it requires a substantial amount of logic circuitry for its implementation. This, of course, is undesirable since it adds to the cost of the system. For example, each of the components 12-21 typically are comprised of several semiconductor chips.
Also, the large amount of circuitry involved in converter 10 adds to the systems complexity thereby making it difficult to debug. For example, if adder 15 fails to propagate an internal carry, that problem would be difficult to isolate since the inputs to the adder are not formed directly but instead are dependent upon the various logical operations that are performed by components 12, 13, 17, 18 and 19.
Accordingly, it is a primary object of the invention to provide an improved circuit for addressing memories with a BCD address.
Another object of the invention is to provide a BCD memory addressing circuit having improved operating speed.
Another object of the invention is to provide a BCD memory addressing circuit that is implemented with only a minimal amount of logic.